LOGIC COMMANDS AND REGISTERS Four registers" />
參數(shù)資料
型號(hào)： MC33889DWR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 38/59頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/CAN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
控制器類(lèi)型： 系統(tǒng)基礎(chǔ)芯片
接口： CAN
電源電壓： 5.5 V ~ 18 V
電流 - 電源： 45mA
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
33889
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:
write to CAN register can end up as write to MCR register, or
write to TIM1 register can end up as write to RCR register
To avoid the previously described behavior, it is recommended to write into the MCR, RCR,
CAN, and IOR registers with the expected configuration, after each RST assertion.
In the application, a RST low pulse leads to an MCU reset and a software restart. By
applying this recommendation, all registers will be written with the expected configuration.
Register Description
Table 10. MCR Register
MCR
D3
D2
D1
D0
$000b
W
MCTR2
MCTR1
MCTR0
R
BATFAIL
VDDTEMP
GFAIL
WDRST
Reset
0
Reset condition
POR, RESET
Table 11. Control Bits
MCTR2
MCTR1
MCTR0
SBC mode
Description
0
Enter/leave debug mode
To enter debug mode, SBC must be in Normal or Standby
mode and BATFAIL (30) must be still at 1. To leave debug
mode, BATFAIL must be at 0.
0
1
Normal
0
1
0
Standby
0
1
Stop, watchdog off (31)
0
1
Stop, watchdog on (31)
1
0
Sleep (32)
1
0
1
Normal
No watchdog running, debug mode
1
0
Standby
1
Stop (33)
Notes
30.
Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3V.
31.
Watchdog ON or OFF depends on the RCR register bit D3.
32.
Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1.
33.
Stop command should be replaced by Stop Watchdog OFF. MCTR2=0, MCTR1= MCTR0=1
Table 12. Status Bits
Status bit
Description
GFAIL
Logic OR of CAN failure, HS1 failure, V2LOW
BATFAIL
Battery fail flag (VSUP < 3.0 V)
VDDTEMP
Temperature prewarning on VDD (latched)
WDRST
Watchdog reset occurred
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