OPERATIONAL MODES CYCLIC SENSE WAKE-UP (CYC" />
參數(shù)資料
型號(hào)： MC33889BDWR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 22/59頁(yè)
文件大小： 0K
描述： IC SYSTEM BASE W/CAN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
控制器類型： 系統(tǒng)基礎(chǔ)芯片
接口： CAN
電源電壓： 5.5 V ~ 18 V
電流 - 電源： 45mA
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0, L1)
The SBC can wake-up from a state change of one of the wake-up input lines (L0, L1), while the external pullup or pulldown
resistor of the switches associated to the wake-up input lines are biased with HS1 VSUP switch. The HS1 switch is activated in
sleep or stop mode from an internal timer. Cyclic sense and forced wake-up are exclusive. If Cyclic sense is enabled, the forced
wake-up can not be enabled.
INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION
In case the Cyclic sense and Lx both level sensitive conditions are use together, the initial value for Lx inputs are sampled in
two cases:
1) When the register LPC[D3 and D0] are set and
2) At cyclic sense event, that is when device is in sleep or stop mode and HS1 is active.
The consequence is that when the device wake up by Lx transition, the new value is sampled as default, then when the device
is set back into low power again, it will automatically wake up.
The user should reset the LPC bits [D3 and D0] to 0 and set them again to the desired value prior to enter sleep or stop
mode.
FORCED WAKE-UP
The SBC can wake-up automatically after a predetermined time spent in sleep or stop mode. Forced wake-up is enabled by
setting bit FWU in the LPC register. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the Cyclic
sense can not be enabled.
CAN WAKE-UP
The device can wake-up from a CAN message. A CAN wake-up cannot be disabled.
SPI WAKE-UP
The device can wake-up by the CS pin in sleep or stop mode. Wake-up is detected by the CS pin transition from a low to high
level. In stop mode this correspond to the condition where the MCU and SBC are both in Stop mode, and when the application
wake-up events come through the MCU.
SYSTEM POWER UP
At power up the device automatically wakes up.
DEVICE POWER UP, SBC WAKE UP
After device or system power up or a wake-up from sleep mode, the SBC enters into “reset mode” then into “normal request
mode”.
BATTERY FALL EARLY WARNING
This function provides an interrupt when the VSUP voltage is below the 6.1 V typical. This interrupt is maskable. A hysteresis
is included. Operation is only in Normal and Stand-by modes. VBAT low state reports in the IOR register.
RESET AND WDOG OPERATION
The following figure shows the reset and watchdog output operations. Reset is active at device power up and wake-up. Reset
is activated in case the VDD1 falls or the watchdog is not triggered. The WDOG output is active low as soon as the reset goes
low and stays low for as long as the watchdog is not properly re-activated by the SPI.
The WDOG output pin is a push pull structure than can drive external components of the application, for instance to signal the
MCU is in a wrong operation. Even if it is internally turned on (low-state), the reset pin can be forced to 5.0 V at 25 °C only, thanks
to its internally limited current drive capability. The WDOG stays low until the Watchdog register is properly addressed through
the SPI.
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