參數(shù)資料
型號: MC33389
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: System Basis Chip with Low Speed Fault Tolerant CAN(帶低速容錯CAN接口的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片與低速容錯CAN(帶低速容錯的CAN接口的系統(tǒng)基片)
文件頁數(shù): 33/35頁
文件大小: 591K
代理商: MC33389
MC33389
33
MC33389
The SBC offers several capabilities to help user debug its
application.
- External bias of V1 and reset pin.
- Turn off of the software watchdog in standby mode.
- Special debug samples with software watchdog disable
at power up (contact local Motorola representative).
Debug And Program Download Into Flash Memory
While the SBC is powered it enters normal request and
expect within the 75ms time period of the NR mode an SPI
tigger word (to enter normal mode and select the W/D time
period). If this does not occurs, the SBC enter sleep mode and
turn off V1.
When the software is been debug, and when using
development tools, it is not always easy to make sure these
events properly. It is thus possible to externally power the V1
line with an external 5V supply, and to force the Reset pin to
V1 or to and external 5V. These can be done at nominal
voltage and temperature. By doing this, 5V is provided to the
MCU Vdd and reset lines.
Under this condition the SBC is not operational. However
the reset pin is pulled low and is sinking 5mA to ground. This
means that the external circuitry which drive reset must have
a current capability higher than 5mA in order to drive the reset
in high state.
Disable Of Software Watchdog In Standby Mode
The software watchdog can be disable in standby mode
only. In order to disable it the following operation must be done:
- Write to MCR register: data 011 (bit 2, bit 1, bit 0)
- Write to MCVR register: data 011 (bit 2, bit 1, bit 0)
Then the SBC enters the standby mode without software
watchdog. However the V2 can not be turn on, and the CAN
cell can not be used.
Special Device
Special components are available to make the debug
even easier. These device has a special behaviour which at
power up disable the watchdog. These device can be
available through marketing only. Contact local Motorola
representative for more detail.
The behaviour of such special parts is as follow:
- At power up (from Vbat =0V), the SBC enters "normal request
mode" and stays in this mode permanently. V1 is on, V2 and V3
off, CAN in Term Vbat. For reference, with MC33389ADW and
MC33389CDH units it stays there 75ms only and go to sleep if no
SPI.
- To get the SBC out on NormalRequest mode, write to
SWCR register any valid data. This will enable the SBC to
enter Normal mode, with V1 and V2 on. Once this is done, the
SBC is controllable through SPI, in the same way as the
normal versions. It can be turned in sleep. After wake up it
enters NR mode (same as after power up described above).
Only difference is that there is no need to refresh the
software watchdog. Internally, the watchdog is running but
when time out elapsed a reset is not generated.
When application debug is advanced enough, it is
possible to enable the W/D-reset function.
To re activated the W/D effect, the VSSR register, bit
VBSR0 (bat fail) must be read (cleared). When this is done,
the W/D and 75ms timer of the NR mode effects are activated.
However, due to re synchronisation, it is likely that at some
point a reset is generated and that the SBC enter reset state
then Normalrequest mode.
When the SBC has had it W/D reactivated it is not possible
to deactivated it again by software. The only way to do this is
to remove battery supply voltage (Vbat < 3V for more than
200us) and then power up the SBC.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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