參數(shù)資料
型號(hào): MC33389
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: System Basis Chip with Low Speed Fault Tolerant CAN(帶低速容錯(cuò)CAN接口的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片與低速容錯(cuò)CAN(帶低速容錯(cuò)的CAN接口的系統(tǒng)基片)
文件頁數(shù): 26/35頁
文件大?。?/td> 591K
代理商: MC33389
MC33389
MOTOROLA
26
MC33389
Table 40.
Table 41.
The information in SPIWU and BUSWU is latched. Bits SPIWU and BUSWU will be reseted by a read operation of the
WUICR register and are set to 0 after a power on reset. A reset of WUICR1 and WUICR0 occurs when RSTB = low.
Table 42. WUISR — Wake-up Input Status Register
This register is used to read back the wake input (L0, L1 or L2) which has cause the SBC to wake up.
Table 43.
In case of a wake-up event, the appropriate bit is set to 1. The bits will be reseted by a read operation of the register. After
power on reset all bits are set to 0.
Table 44. WUIRTI — Wake-up Input Real-time Information
This register reports the real time information on the state (high or low) of the L0, L1 and L2 inputs.
The bits WUIRTI2-0 contain the real time logic value coming from the wake-up inputs (0 mean input below threshold, 1 mean
input above threshold. Typical threshold is 3.5V).
Table 45. OTSR — Overtemperature Status Register
WUICR1
WUICR0
Description
Comments
0
0
Wake-up inputs disabled
0
1
Positive edge sensitive
1
0
Negative edge sensitive
1
1
Positive and negative sensitive
SPIWU
BUSWU
Description
Comments
0
0
No wake-up events
X
1
Wake-up event on CAN bus
1
X
Wake-up event on SPI bus
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
WUISR
$00F
R
WUISR2
WUISR1
WUISR0
W
RESET
0
0
0
WUISR2
WUISR1
WUISR0
Comments
0
0
0
No Event on Wake-up Inputs
X
X
1
Event on L0
X
1
X
Event on L1
1
X
X
Event on L2
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
WUIRTI
$011
R
WUIRTI2
WUIRTI1
WUIRTI0
W
RESET
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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