參數(shù)資料
型號(hào): MC100EP52MNR4G
廠商: ON SEMICONDUCTOR
元件分類(lèi): 通用總線(xiàn)功能
英文描述: 3.3V / 5V ECL Differential Data and Clock D Flip−Flop
中文描述: 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, DSO8
封裝: LEAD FREE, DFN-8
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 168K
代理商: MC100EP52MNR4G
MC10EP52, MC100EP52
http://onsemi.com
6
Table 10. 100EP DC CHARACTERISTICS, NECL
V
CC
= 0 V, V
EE
=
5.5 V to
3.0 V (Note 17)
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
20
34
44
20
35
45
20
37
47
mA
V
OH
Output HIGH Voltage (Note 18)
1145
1020
895
1145
1020
895
1145
1020
895
mV
V
OL
Output LOW Voltage (Note 18)
1945
1820
1695
1945
1820
1695
1945
1820
1695
mV
V
IH
Input HIGH Voltage (Single
Ended)
1225
880
1225
880
1225
880
mV
V
IL
Input LOW Voltage (Single
Ended)
1945
1625
1945
1625
1945
1625
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
CC
.
18.All loading with 50 to V
2.0 V.
19.V
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
=
3.0 V to
5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 20)
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
OUTpp
Output Voltage Amplitude @ 3.0 GHz
(Figure 2)
630
750
610
730
520
640
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
CLK, CLK
>Q, Q
250
300
350
280
330
380
310
360
410
ps
t
S
t
H
Setup Time
Hold Time
50
0
50
0
50
0
ps
t
JITTER
CLOCK Random Jitter (RMS)
(Figure 2)
0.2
1
0.2
1
0.2
1
ps
V
PP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
t
r
t
f
Output Rise/Fall Times
(20%
80%)
Q, Q
70
110
170
80
120
180
90
130
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to V
CC
2.0 V.
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