參數(shù)資料
型號(hào): M5482B7
廠商: 意法半導(dǎo)體
英文描述: Capacitors
中文描述: LED顯示驅(qū)動(dòng)器
文件頁(yè)數(shù): 3/6頁(yè)
文件大小: 97K
代理商: M5482B7
STATIC ELECTRICAL CHARACTERISTICS
(T
amb
within operating range, V
DD
= 4.75V to 13.2V, V
SS
= 0V,unless otherwise specified)
Symbol
V
DD
I
DD
V
I
Parameter
Test Conditions
Min.
4.75
Typ.
Max.
13.2
7
Unit
V
mA
Supply Voltage
Supply Current
Input Voltages
Logical "0" Level
Logical "1" Level
V
DD
= 13.2 V
±
10
μ
A Input Bias
4.75
V
5.25
V
DD
> 5.25
– 0.3
2.2
V
DD
– 2
0
3
0.8
V
DD
V
DD
0.75
4.3
V
V
V
I
B
V
B
Brightness Input Current (note 2)
Brightness Input Voltage (pin 9)
mA
V
Input Current = 750
μ
A
T
amb
= 25
C
V
O(off)
I
O
Off State Output Voltage
Output Sink Current (note 3)
Segment OFF
Segment ON
13.2
V
V
O
= 3 V
V
= 1 V (note 4)
Brightness In. = 0
μ
A
Brightness In. = 100
μ
A
Brightness In. = 750
μ
A
0
2
12
0
2.7
15
10
10
4
25
0.5
±
20
μ
A
μ
A
mA
mA
MHz
%
f
clock
I
O
Input Clock Frequency
Output Matching (note 1)
Notes :
1. Output matching is calculated as the percent variation from I
+ I
/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
3. Absolute maximum for each output should be limited to 40 mA.
4. The V
O
voltage should be regulated by the user.
5
FUNCTIONAL DESCRIPTION
The M5482 uses the M5451 die which is packaged
to operate 2-digit alphanumeric displays with mini-
mal interface with the display and the data source.
Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial
data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer
without an additional load signal.
The 35 data bits are latched after the 36th bit is
complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the
serial data bits differ from the previous time. Display
brightness is determined by control of the output
current for LED displays. A 1nF capacitor should be
connected to brightness control, Pin 9, to prevent
possible oscillations.
A block diagram is shown in Figure 1. The output
current is typically 20 times greater than the current
into Pin 9, which is set by an external variable
resistor.
There is an internal limiting resistor of 400
nomi-
nal value.
Figure 2 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
36
BIT 34
BIT 35
CLOCK
DATA
LOAD
(INTERNAL)
RESET
(INTERNAL)
START
BIT 1
1
5
Figure 2 :
Input Data Format
M5482
3/6
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