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參數(shù)資料
| 型號： | M48Z19-100PC1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CMOS 8K x 8 ZEROPOWER SRAM |
| 中文描述： | 的CMOS 8K的× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 122K |
| 代理商： | M48Z19-100PC1 |
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
–40 to 85
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Note:
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
Mode
V
CC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
X
High Z
Standby
Deselect
X
V
IL
X
X
High Z
Standby
Write
V
IL
V
IH
X
V
IL
D
IN
Active
Read
V
IL
V
IH
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO
X
X
X
X
High Z
Battery Back-up Mode
Note
: X = V
IH
or V
IL
Table 3. Operating Modes
A1
A0
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
W
DQ5
DQ4
DQ3
A12
INT
VCC
AI01185
M48Z09
M49Z19
8
9
10
11
12
13
14
1
2
3
4
5
6
7
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
The M48Z09,19 button cell has sufficient capacity
and storage life to maintain data for an accumu-
lated time period of at least 11 years in the absence
of power over the operating temperature range.
The M48Z09,19 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z09,19 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system opera-
tion brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
DESCRIPTION
(cont’d)
2/13
M48Z09, M48Z19
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