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參數(shù)資料
| 型號(hào)： | M48Z08-100MH6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Kbit 8Kb x 8 ZEROPOWER SRAM |
| 中文描述： | 64千位的8kB × 8 ZEROPOWER的SRAM |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | M48Z08-100MH6 |
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Symbol
Parameter
M48Z08 / M48Z18
Unit
-100
Min
Max
t
AVAV
Write Cycle Time
100
ns
t
AVWL
Address Valid to Write Enable Low
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
ns
t
WLWH
Write Enable Pulse Width
80
ns
t
ELEH
Chip Enable Low to Chip Enable High
80
ns
t
WHAX
Write Enable High to Address Transition
10
ns
t
EHAX
Chip Enable High to Address Transition
10
ns
t
DVWH
Input Valid to Write Enable High
50
ns
t
DVEH
Input Valid to Chip Enable High
30
ns
t
WHDX
Write Enable High to Input Transition
5
ns
t
E1HDX
Chip Enable High to Input Transition
5
ns
t
WLQZ (1, 2)
Write Enable Low to Output Hi-Z
50
ns
t
AVWH
Address Valid to Write Enable High
80
ns
t
AVEH
Address Valid to Chip Enable High
80
ns
t
WHQX (1, 2)
Write Enable High to Output Transition
10
ns
Notes:
1. C
= 30pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Table 10. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
READ MODE
The M48Z08/18 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 65,536 locations in the
static storage array. Thus, the unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48Z08/18 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E.
A write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs t
WLQZ
after W falls.
7/18
M48Z08, M48Z18
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