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參數(shù)資料
| 型號(hào)： | M48T248V-70PM1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | FILTER SAW 312.2MHZ REMOTE SMD |
| 中文描述： | 5.0或3.3V，1024K與幻象計(jì)時(shí)器的SRAM |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | M48T248V-70PM1TR |
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M48T248Y, M48T248V
OPERATION MODES
Table 6. Operating Modes
Note: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage
1. See Table 9, page 14 for details.
READ
A READ cycle executes whenever WRITE Enable
(WE) is high and Chip Enable (CE) is low (see Fig-
ure 6). The distinct address defined by the 19 ad-
dress inputs (A0-A18) specifies which of the 512K
bytes of data is to be accessed. Valid data will be
accessed by the eight data output drivers within
the specified Access Time (t
ACC
) after the last ad-
dress input signal is stable, the CE and OE access
times, and their respective parameters are satis-
fied. When CE t
ACC
and OE t
ACC
are not satisfied,
then data access times must be measured from
the more recent CE and OE signals, with the limit-
ing parameter being t
CO
(for CE) or t
OE
(for OE) in-
stead of address access.
WRITE
WRITE Mode (see Figure 7, page 10 and Figure 8,
page 11) occurs whenever CE and WE signals are
low (after address inputs are stable). The most re-
cent falling edge of CE and WE will determine
when the WRITE cycle begins (the earlier, rising
edge of CE or WE determines cycle termination).
All address inputs must be kept stable throughout
the WRITE cycle. WE must be high (inactive) for a
minimum recovery time (t
WR
) before a subsequent
cycle is initiated. The OE control signal should be
kept high (inactive) during the WRITE cycles to
avoid bus contention. If CE and OE are low (ac-
tive), WE will disable the outputs for Output Data
WRITE Time (t
ODW
) from its falling edge.
Figure 6. Memory READ Cycle
Note: WE is high for a READ cycle.
Mode
V
CC
CE
OE
WE
DQ7-DQ0
Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
V
IH
X
X
High-Z
Standby
WRITE
V
IL
X
V
IL
D
IN
Active
READ
V
IL
V
IL
V
IH
D
OUT
Active
READ
V
IL
V
IH
V
IH
High-Z
Active
Deselect
V
SO
to V
PFD
(min)
(1)
X
X
X
High-Z
CMOS Standby
Deselect
≤
V
SO(1)
X
X
X
High-Z
Battery Back-Up
DQ0 - DQ7
ADDRESSES
OE
CE
DATA OUTPUT
VALID
tOD
tODO
tOE
tRC
tCO
tACC
tCOE
tCOE
tOH
AI04230
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T248V-85PM1 | FILTER SAW 313.85MHZ REMOTE SMD |
| M48T248V | 5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248V-85PM1TR | 5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248VPM | 5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T251V-70PM1 | 5.0 or 3.3V, 4096K TIMEKEEPER SRAM with PHANTOM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T248V-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248V-85PM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248VPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248Y-70PM1 | 功能描述:實(shí)時(shí)時(shí)鐘 1M (128Kx8) 70ns RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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