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參數(shù)資料
| 型號(hào)： | M48T212YMH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V/3.3V TIMEKEEPER[ CONTROLLER |
| 中文描述： | 5V/3.3V計(jì)時(shí)[控制器 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 150K |
| 代理商： | M48T212YMH |
11/23
M48T212Y, M48T212V
Table 11. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C)
Note: 1. C
= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T212Y
M48T212V
Unit
-70
-85
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
85
ns
t
AVWL
Address Valid to Write Enable Low
0
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
0
ns
t
WLWH
Write Enable Pulse Width
45
55
ns
t
ELEH
Chip Enable Low to Chip Enable High
50
60
ns
t
WHAX
Write Enable High to Address Transition
0
0
ns
t
EHAX
Chip Enable High to Address Transition
0
0
ns
t
DVWH
Input Valid to Write Enable High
25
30
ns
t
DVEH
Input Valid to Chip Enable High
25
30
ns
t
WHDX
Write Enable High to Input Transition
0
0
ns
t
EHDX
Chip Enable High to Input Transition
0
0
ns
t
WLQZ(1,2)
Write Enable Low to Output High-Z
20
25
ns
t
AVWH
Address Valid to Write Enable High
55
65
ns
t
AVEH
Address Valid to Chip Enable High
55
65
ns
t
WHQX(1,2)
Write Enable High to Output Transition
5
5
ns
DATA RETENTION MODE
With valid V
CC
applied, the M48T212Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
V
CC
falls between V
PFD
(max) and V
PFD
(min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until V
CC
returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1
CON
and E2
CON
to a high level.
This level is within 0.2 volts of the V
BAT
. E1
CON
and E2
CON
will remain at this level as long as V
CC
remains at an out-of tolerance condition.
When V
CC
falls below the level of the battery
(V
BAT
), power input is switched from the V
CC
pin
to the SNAPHAT battery and the clock registers
and external SRAM are maintained from the at-
tached batterysupply. All outputs become highim-
pedance. The V
OUT
pin is capable of supplying
100
μ
A of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when V
CC
returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting
E1
CON
or E2
CON
.
The RST signal also remains active during this
time (see Figure 5).
Note:
Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of anSRAM to use.The SRAM mustbe de-
signed in a way where the chip enable input dis-
ables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be Don’t
Care once V
CC
falls below V
PFD
(min). The SRAM
should also guarantee data retention down to
V
CC
= 2.0V. The chip enable access time must be
sufficient to meet the system needs with the chip
enable output propagation delays included.
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| M48T212Y-85MH1TR | Multiconductor Cable; Number of Conductors:7; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Conductor Material:Copper; Temperature Max:80 C RoHS Compliant: Yes |
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| M48T212YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V/3.3V TIMEKEEPER[ CONTROLLER |
| M48T248V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248V-70PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248V-70PM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
| M48T248V-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM |
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