參數(shù)資料
型號(hào): M48T212Y-85MH6
廠(chǎng)商: 意法半導(dǎo)體
英文描述: Shielded Multiconductor Cable; Number of Conductors:7; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid RoHS Compliant: Yes
中文描述: 5V/3.3V計(jì)時(shí)[控制器
文件頁(yè)數(shù): 10/23頁(yè)
文件大?。?/td> 150K
代理商: M48T212Y-85MH6
M48T212Y, M48T212V
10/23
Figure 8. Write Cycle Timing: RTC Control Signals
AI02641
W
DQ0-DQ7
G
DATA IN
VALID
ADDRESS
tAVAV
E
tAVEH
tAVAV
tAVAV
WRITE
WRITE
READ
DATA OUT
VALID
DATA OUT
VALID
tAVWH
tAVQV
tWLWH
tWHDX
tWHAX
tWHQX
tWLQZ
tDVWH
tGLQV
tEHQZ
tDVEH
DATA IN
VALID
tELEH
tEHAX
tAVEL
tEHDX
tAVWL
WRITE MODE
The M48T212Y/V is in the Write Mode whenever
W (Write Enable) and E(Chip Enable) are in a low
state afterthe address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W orE. A write is terminated by the
earlier rising edge of W or E. The addresses must
be heldvalid throughout the cycle. E orW must re-
turn high for a minimum of t
EHAX
from Chip Enable
or t
WHAX
from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
t
DVWH
priorto the end of write and remain valid for
t
WHDX
afterward.
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on Eand G alow onW will
disable the outputs t
WLQZ
after W falls.
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data willbe written into the device. When EXis low
(and E is high) an external SRAM location is se-
lected.
Note:
Care should be taken to avoid takingboth E
and EX low simultaneously to avoid bus conten-
tion.
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