參數(shù)資料
型號: M48T08PC
廠商: 意法半導體
英文描述: 64 Kbit 8Kb x 8 TIMEKEEPER SRAM
中文描述: 64千位的8kB × 8計時器的SRAM
文件頁數(shù): 6/27頁
文件大?。?/td> 398K
代理商: M48T08PC
M48T08, M48T08Y, M48T18
6/27
OPERATION MODES
As
Figure 6., page 5
shows, the static memory ar-
ray and the quartz-controlled clock oscillator of the
M48T08/18/08Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with
addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT READ/WRITE memory
cells. The M48T08/18/08Y includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below the Battery Back-up Switchover Voltage
(V
SO
), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
Table 2. Operating Modes
Note: X = V
IH
or V
IL
;
V
SO
= Battery Back-up Switchover Voltage.
1. See
Table 11., page 20
for details.
Mode
V
CC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
4.75 to 5.5V
or
4.5 to 5.5V
V
IH
X
X
X
High Z
Standby
Deselect
X
V
IL
X
X
High Z
Standby
WRITE
V
IL
V
IH
X
V
IL
D
IN
Active
READ
V
IL
V
IH
V
IL
V
IH
D
OUT
Active
READ
V
IL
V
IH
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(1)
X
X
X
X
High Z
CMOS Standby
Deselect
V
SO(1)
X
X
X
X
High Z
Battery Back-up Mode
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