參數(shù)資料
型號(hào): M41T81SMY6T
廠商: 意法半導(dǎo)體
英文描述: Serial Access Real-Time Clock with Alarms
中文描述: 串行訪問(wèn)實(shí)時(shí)時(shí)鐘與鬧鐘
文件頁(yè)數(shù): 13/29頁(yè)
文件大?。?/td> 438K
代理商: M41T81SMY6T
13/29
M41T81S
Calibrating the Clock
The M41T81S is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768Hz. The
devices are tested not exceed ±35 ppm (parts per
million) oscillator frequency error at 25
o
C, which
equates to about +1.9 to –1.1 minutes per month
(see
Figure 12., page 14
). When the Calibration
circuit is properly employed, accuracy improves to
better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with tem-
perature. The M41T81S design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in
Figure
13., page 14
. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Calibration Register. Adding counts speeds
the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Calibration Register 08h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register (see
Figure
13., page 14
). Assuming that the oscillator is run-
ning at exactly 32,768Hz, each of the 31 incre-
ments in the Calibration byte would represent
+10.7 or –5.35 seconds per month which corre-
sponds to a total range of +5.5 or –2.75 minutes
per month.
Two methods are available for ascertaining how
much calibration a given M41T81S may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-
ER
CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT/SQW pin. The pin will toggle at
512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the
Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0'
and the Watchdog Register (09h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature.
For
example,
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
The IRQ/FT/OUT/SQW pin is an open drain output
which requires a pull-up resistor to V
CC
for proper
operation. A 500-10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
a
reading
of
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