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參數(shù)資料
| 型號(hào)： | M41T81SMY6F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Access Real-Time Clock with Alarms |
| 中文描述： | 串行訪問實(shí)時(shí)時(shí)鐘與鬧鐘 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 438K |
| 代理商： | M41T81SMY6F |
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M41T81S
Figure 18. Bus Timing Requirements Sequence
Table 13. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Sym
Parameter
(1)
Min
Typ
Max
Units
f
SCL
SCL Clock Frequency
0
400
kHz
t
LOW
Clock Low Period
1.3
μs
t
HIGH
Clock High Period
600
ns
t
R
SDA and SCL Rise Time
300
ns
t
F
SDA and SCL Fall Time
300
ns
t
HD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
t
SU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
t
SU:DAT(2)
Data Setup Time
100
ns
t
HD:DAT
Data Hold Time
0
μs
t
SU:STO
STOP Condition Setup Time
600
ns
t
BUF
Time the bus must be free before a new
transmission can start
1.3
μs
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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