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參數(shù)資料
| 型號： | M41T81MY6TR |
| 廠商： | 意法半導體 |
| 英文描述： | SERIAL ACCESS RTC WITH ALARMS |
| 中文描述： | 串行訪問時鐘用鬧鐘 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 386K |
| 代理商： | M41T81MY6TR |
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M41T81
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to tog-
gle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit, SQWE Bit, and Watch-
dog Register are not set, the IRQ/FT/OUT/SQW
pin becomes an output driver that reflects the con-
tents of D7 of the Control Register. In other words,
when D7 (OUT Bit) and D6 (FT Bit) of address lo-
cation 08h are a '0,' then the IRQ/FT/OUT/SQW
pin will be driven low.
Note:
The IRQ/FT/OUT/SQW pin is an open drain
which requires an external pull-up resistor.
Preferred Initial Power-on Default
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watch-
dog Register; AFE; ABE; SQWE; and FT. The fol-
lowing bits are set to a '1' state: ST; OUT; and HT
(see Table 13, page 21).
Table 13. Preferred Default Values
Note: 1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
Condition
ST
HT
Out
FT
AFE
SQWE
ABE
WATCHDOG
Register
(1)
Initial Power-up
(2)
1
1
1
0
0
0
0
0
Subsequent Power-up (with battery
back-up)
(3)
UC
1
UC
0
UC
UC
UC
0
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| M41T81SM6ET | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Real-Time Clock with Alarms |
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