參數(shù)資料
型號: M41T81M
廠商: 意法半導體
英文描述: SERIAL ACCESS RTC WITH ALARMS
中文描述: 串行訪問時鐘用鬧鐘
文件頁數(shù): 13/28頁
文件大小: 386K
代理商: M41T81M
13/28
M41T81
Figure 15. Alternative READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 16, page 13. Following the START con-
dition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T81 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 13, page 12 and again after it has re-
ceived the word address and each data byte.
Figure 16. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
A
S
A
A
A
N
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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相關代理商/技術參數(shù)
參數(shù)描述
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