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參數(shù)資料
| 型號： | M41T56MH6F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| 中文描述： | 512位（64位× 8）串行SRAM的訪問計時器 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 346K |
| 代理商： | M41T56MH6F |
M41T56
10/24
Figure 12. Alternative READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41T56 slave receiver. Bus protocol is shown
in
Figure 13., page 10
. Following the START con-
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address A
n
will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure
10
).
Data Retention Mode
With valid V
CC
applied, the M41T56 can be ac-
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T56 will automatically deselect, write protect-
ing itself when V
CC
falls between V
PFD
(max) and
V
PFD
(min). This is accomplished by internally in-
hibiting access to the clock registers and SRAM.
When V
CC
falls below the Battery Back-up
Switchover Voltage (V
SO
), power input is switched
from the V
CC
pin to the battery and the clock reg-
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up,
when V
CC
returns to a nominal value, write protec-
tion continues for t
REC
.
For a further more detailed review of battery life-
time calculations, please see Application Note
AN1012.
Figure 13. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
A
S
A
A
A
N
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
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| M41T56MH6E | 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| M41T56MH6 | 512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41T56MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit (64 bit x8) Serial Access TIMEKEEPER SRAM |
| M41T56SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 bit 64b x8 Serial Access TIMEKEEPER SRAM |
| M41T60 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial Access Real-Time Clock |
| M41T60_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
| M41T60_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock |
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