參數(shù)資料
型號(hào)： M25P40SVMN6P/4
廠商： NUMONYX
元件分類： PROM
英文描述： 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件頁(yè)數(shù)： 21/57頁(yè)
文件大?。?/td> 1160K
代理商： M25P40SVMN6P/4
Instructions
M25P40
28/57
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Instruction times,
.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
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M25P40SVMN3G/4A 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
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相關(guān)代理商/技術(shù)參數(shù)
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M25P40-VMB6TPB TR 制造商:Micron Technology Inc 功能描述:IC FLASH 4MBIT 75MHZ 8UFDFPN
M25P40-VMB6Txx 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Micron M25P40 Serial Flash Embedded Memory
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