參數(shù)資料
型號(hào): M25P40SVMN6P/4
廠商: NUMONYX
元件分類: PROM
英文描述: 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件頁(yè)數(shù): 16/57頁(yè)
文件大?。?/td> 1160K
代理商: M25P40SVMN6P/4
M25P40
Instructions
23/57
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 10.
Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
2
1
3456789 10 11 12 13 14 15
Instruction
0
AI02031E
Q
7
6543210
Status Register Out
High Impedance
MSB
7
6543210
Status Register Out
MSB
7
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