- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384604 > LMX2487 (National Semiconductor Corporation) 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL PDF資料下載
參數(shù)資料
| 型號： | LMX2487 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | 為3.0 GHz - 6.0 GHz的高性能Δ-Σ低功耗雙PLLatinum⑩頻率合成器與整數(shù)的3.0 GHz鎖相環(huán) |
| 文件頁數(shù)： | 21/37頁 |
| 文件大小： | 856K |
| 代理商： | LMX2487 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
Functional Description
(Note 8)
(Continued)
CE Pin
Low
RF_PD
X
ATPU
Bit Enabled +
Write to RF
N Counter
X
PLL State
Powered Down
(Asynchronous)
Powered Up
Powered Up
Powered Down
( Asynchronous )
High
High
High
X
0
1
Yes
No
No
1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of
e
. To indicate a locked state
(Lock = HIGH) the phase error must be less than the
e
RC
delay for 5 consecutive reference cycles. Once in lock (Lock
= HIGH), the RC delay is changed to approximately
δ
. To
indicate an out of lock state (Lock = LOW), the phase error
must become greater
δ
. The values of
e
and
δ
are dependent
on which PLL is used and are shown in the table below:
PLL
RF
IF
e
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for
both PLLs, an unlocked (LOW) condition is shown whenever
either one of the PLLs is determined to be out of lock.
20154704
L
www.national.com
21
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2487SQ | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQX | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX3161 | Single Chip Radio Transceiver(單芯片無線電收發(fā)器) |
| LMX3161VBH | Single Chip Radio Transceiver |
| LMX3161VBHX | Single Chip Radio Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:1.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487E-EVM | 功能描述:EVAL MODULE FOR LMX2487 制造商:texas instruments 系列:PLLatinum?? 零件狀態(tài):在售 類型:頻率合成器 頻率:3GHz ~ 7.5GHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:LMX2487E 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| LMX2487ESQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。