M
4-Pin, Low-Power
μP Reset Circuits with Manual Reset
4
_______________________________________________________________________________________
Pin Description
Applications Information
Manual Reset Input
Many μP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on
MR
asserts reset. Reset remains asserted while
MR
is low,
and for the reset active timeout period after
MR
returns
high.
MR
has an internal 20k
pullup resistor, so it can
be left unconnected if not used. Connect a normally
open momentary switch from
MR
to GND to create a
manual reset function; external debounce circuitry is
not required.
Interfacing to μPs with
Bidirectional Reset Pins
Since the
RESET
output on the MAX6805 is open-drain,
this device interfaces easily with μPs that have bidirec-
tional reset pins, such as the Motorola 68HC11.
Connecting the μP supervisor
’
s
RESET
output directly
to the microcontroller
’
s (μC
’
s)
RESET
pin with a single
pullup resistor allows either device to assert reset
(Figure 1).
Negative-Going V
CC
Transients
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration, negative-going
V
CC
transients (glitches). The
Typical Operating
Characteristics
show the Maximum Transient Duration
vs. Reset Comparator Overdrive graph. The graph
shows the maximum pulse width that a negative-going
V
CC
transient may typically have without issuing a reset
signal. As the amplitude of the transient increases, the
maximum allowable pulse width decreases.
Ensuring a Valid Reset Output
down to V
CC
= 0
When V
CC
falls below 1V and approaches the minimum
operating voltage of 0.7V, push/pull-structured reset
sinking (or sourcing) capabilities decrease drastically.
High-impedance CMOS-logic inputs connected to the
RESET
pin can drift to indeterminate voltages. This
does not present a problem in most cases, since most
V
CC
V
CC
GND
MAX6805
RESET
MR
V
CC
GND
RESET
MOTOROLA
68HCXX
μ
P
100k
Figure 1. Interfacing to μPs with Bidirectional Reset Pins
PIN
MAX6803
MAX6804
MAX6805
1
NAME
FUNCTION
1
GND
Ground
—
2
RESET
Active-Low Reset Output.
RESET
is asserted while V
CC
is below the reset
threshold, or while
MR
is asserted.
RESET
remains asserted for a reset
timeout period (t
RP
) after V
CC
rises above the reset threshold or
MR
is
deasserted.
RESET
on the MAX6804 is push/pull.
RESET
on the MAX6805
is open-drain.
Active-High Reset Output. RESET is asserted high while V
CC
is below the
reset threshold or while
MR
is asserted, and RESET remains asserted for a
reset timeout period (t
RP
) after V
CC
rises above the reset threshold or
MR
is deasserted. RESET on the MAX6803 is push/pull.
RESET
—
2
3
3
MR
Manual Reset Input. A logic low on
MR
asserts reset. Reset remains
asserted as long as
MR
is low, and for the reset timeout period (t
RP
) after
MR
goes high. Leave unconnected or connect to V
CC
if not used.
Supply Voltage Input
V
CC
4
4