參數(shù)資料
型號: KSZ8873MLL AM TR
廠商: Micrel Inc
文件頁數(shù): 74/115頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
61
Revision 1.6
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0 (Continued)
Bit
Name
R/W
Description
Default
4-3
Port-Based
Priority
Classification
R/W
=00, Ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=01, Ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=10, Ingress packets on port will be
classified as priority 2 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=11, Ingress packets on port will be
classified as priority 3 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time.
The OR’ed result of 802.1p and DSCP overwrites the port priority.
00
2
Tag Insertion
R/W
=1, When packets are output on the port, the switch will add 802.1p/q tags to
packets without 802.1p/q tags when received. The switch will not add tags to
packets already tagged. The tag inserted is the ingress port’s “port VID”.
=0, Disable tag insertion
Note: For the tag insertion available, the register 194 bits [5-0] have to be set
first.
0
1
Tag Removal
R/W
=1, When packets are output on the port, the switch will remove 802.1p/q tags
from packets with 802.1p/q tags when received. The switch will not modify
packets received without tags.
=0, Disable tag removal
0
TXQ Split Enable
R/W
=1, Split TXQ to 4 queue configuration. It cannot be enable at the same time
with split 2 queue at register 18, 34,50 bit 7.
=0, No split, treated as 1 queue configuration
0
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