參數(shù)資料
型號: KSZ8873MLL AM TR
廠商: Micrel Inc
文件頁數(shù): 113/115頁
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓模塊: KSZ8873 Ethernet Switches
標準包裝: 1,000
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
97
Revision 1.6
Table 21. Format of “All Port Dropped Packet” MIB Counters
Bit
Name
R/W
Description
Default
30-16
Reserved
N/A
Reserved
N/A
15-0
Counter Value
RO
Counter Value
0
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 22.
Table 22. “All Port Dropped Packet” MIB Counters
Offset
Counter Name
Description
0x100
Port1 TX Drop Packets
TX packets dropped due to lack of resources
0x101
Port2 TX Drop Packets
TX packets dropped due to lack of resources
0x102
Port3 TX Drop Packets
TX packets dropped due to lack of resources
0x103
Port1 RX Drop Packets
RX packets dropped due to lack of resources
0x104
Port2 RX Drop Packets
RX packets dropped due to lack of resources
0x105
Port3 RX Drop Packets
RX packets dropped due to lack of resources
Examples:
1.
MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counters selected
Write to reg. 122 (0x7A) with 0x0e
// Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow valid
bit [30] // If bit 30 = 0, restart (reread) from this register counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2.
MIB Counter Read (Read port 2 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e
// Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow valid
bit [30] // If bit 30 = 0, restart (reread) from this register counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
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