參數(shù)資料
型號(hào)： KSZ8851-16MLL TR
廠(chǎng)商： Micrel Inc
文件頁(yè)數(shù)： 61/84頁(yè)
文件大小： 0K
描述： IC MAC CTLR 1PORT W/BUS 48LQFP
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1,000
控制器類(lèi)型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線(xiàn)
電源電壓： 1.8V，2.5V，3.3V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
PIC16F7X
DS30325B-page 62
2002 Microchip Technology Inc.
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
SDI must have TRISC<4> set
SDO must have TRISC<5> cleared
SCK (Master mode) must have TRISC<3>
cleared
SCK (Slave mode) must have TRISC<3> set
SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
.
Read
Write
Internal
Data Bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Peripheral OE
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
3: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
‘0100’), the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC controls the
state
that
is
read
back
from
the
TRISC<5> bit (see Section 4.3 for infor-
mation on PORTC). If Read-Modify-Write
instructions, such as BSF are performed
on the TRISC register while the SS pin is
high, this will cause the TRISC<5> bit to
be set, thus disabling the SDO output.
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