參數(shù)資料
型號： KSZ8851-16MLL TR
廠商： Micrel Inc
文件頁數(shù)： 49/84頁
文件大?。?/td> 0K
描述： IC MAC CTLR 1PORT W/BUS 48LQFP
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1,000
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
2002 Microchip Technology Inc.
DS30325B-page 51
PIC16F7X
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro Mid-Range MCU Family Reference
Manual (DS33023).
7.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
a write to the TMR2 register
a write to the T2CON register
any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
Comparator
TMR2
Sets Flag
TMR2 reg
Output(1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
1:1 to 1:16
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
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