參數(shù)資料
型號(hào): KSZ8851-16MLL TR
廠商: Micrel Inc
文件頁(yè)數(shù): 19/84頁(yè)
文件大?。?/td> 0K
描述: IC MAC CTLR 1PORT W/BUS 48LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 1,000
控制器類(lèi)型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
26
Revision 2.2
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 12KB for RXQ and 6KB for TXQ of memory with back-to-back, non-blocking frame transfer performance.
It provides a group of control registers for system control, frame status registers for current packet transmit/receive status,
and interrupts to inform the host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 5. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon
whether hardware CRC checksum generation is enabled in TXCR (bit 1) register.
Multiple frames can be pipelined in the receive queue as long as there is enough queue memory, thus avoiding overrun.
For each transmitted frame, the transmit status information for the frame is located in the TXSR (0x72) register.
Packet Memory Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Control Word
(High byte and low byte need to swap in Big-Endian mode)
2
Byte Count
(High byte and low byte need to swap in Big-Endian mode)
4 - up
Transmit Packet Data
(maximum size is 2000)
Table 5. Frame Format for Transmit Queue
Since packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of the
packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the TX
queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word
aligned. Each control word corresponds to one TX packet. Table 6 gives the transmit control word bit fields.
Bit
Description
15
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8851-16MLL sets the transmit interrupt after the present frame has been transmitted.
14-6
Reserved.
5-0
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status information in the transmit
status register.
Table 6. Transmit Control Word Bit Fields
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