參數(shù)資料
型號(hào)： KSZ8841-16MBLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 35/105頁(yè)
文件大小： 0K
描述： IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝： 260
控制器類(lèi)型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
35
M9999-102207-1.6
Signal
Type
(1)
Function
For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that
the wait states are inserted by system logic (memory) not by KSZ8841M.
BCLK
I
Bus Clock
Asynchronous Transfer Signals
RDN
I
Asynchronous Read
WRN
I
Asynchronous Write
ARDY
O
Asynchronous Ready
This signal is asserted (Low) to insert wait states.
Note 1: I = Input. O = Output. I/O = Bi-directional.
Table 2. Bus Interface Unit Signal Grouping
Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of
ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Note: If the local device decoder is used in either synchronous or asynchronous transfers, LDEVN will be asserted to
indicate that the KSZ8841M is successfully targeted. The signal LDEVN is a combinatorial decode of AEN and A[15:4].
Asynchronous Interface
For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the
synchronous dedicated signals CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level
throughout the entire asynchronous transfer.
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three
major ways of interfacing with the system (host) are.
1.
Interfacing with the system/host relying on local device decoding and having stable address throughout the whole
transfer: The typical example for this application is ISA-like bus interface using latched address signals as shown
in Figure 13. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. The
host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.
Interfacing with the system/host relying on local device decoding but not having stable address throughout the entire
transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in the Figure 14. This
type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies
with AEN to determine if the KSZ8841M device is the intended target. The data transfer is the same as the first case.
Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only).
The typical example for this application is for an embedded processor having a central decoder on the system board or
within the processor. Connecting the chip select (CS) from system/host to DATACSN bypasses the local device decoder.
When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N, BE1N, and BE0N
are ignored as shown in the Figure 15. No other registers can be accessed by asserting DATACSN. The data transfer is
the same as in the first case. Independent of the type of asynchronous interface used. To insert a wait state, the BIU will
assert ARDY to prolong the cycle.
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