參數(shù)資料
型號： KSZ8695X-EVAL
廠商： Micrel Inc
文件頁數(shù)： 19/39頁
文件大?。?/td> 0K
描述： KIT EVAL KSZ8695X EXPERIMENT
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8695X
主要屬性： 單芯片網(wǎng)關(guān)解決方案
已供物品： 板
相關(guān)產(chǎn)品： 576-1025-ND - IC SWITCH 10/100 5PORT 208PQFP
其它名稱： 576-1624
Micrel, Inc.
KS8695X
June 2006
26
M9999-060106
Address Map and Register Description
Memory Map
Upon power up, the KS8695X memory map is configured as shown below.
Address Range
Region
Description
0x03FF0000-0x03FFFFFF
64KB
KS8695PX System Conguration Register Space
0x02000000-0x03FEFFFF
32MB
Not Congured
0x00000000-0x01FFFFFF
32MB
Flash Bank 0
Memory Map Example
The default base address for the KS8695X system configuration registers is 0x03ff0000. After power up, the user is free
to remap the memory for their specific application. The following is an example of the memory space remapped for
operation.
Address Range
Region
Description
0x03FF0000-0x03FFFFFF
64KB
KS8695PX System Conguration Register Space
0x02900000-0x03FEFFFF
23MB
Spare (External I/O)
0x02100000-0x028FFFFF
8MB
FLASH
0x00100000-0x020FFFFF
32MB
SDRAM
0x00000000-0x0007FFFF
512KB
SRAM
Register Description
The KS8695X system configuration registers (SCRs) are located in a block of 64KB in the host memory address space.
After power up and initialization, the user can remap the SCRs to a desired offset. The SCRs are 32 bits wide. They are
32 bit word-aligned and must be accessed using word instructions. A description of the KS8695X system configuration
registers follows. For bit definitions, please see the detailed "Register Description" section.
Address
Description
Mode
Size
System Registers
0x0000
System Configuration Register
R/W
[31:0]
0x0004
System Clock and Bus Control Register
R/W
[31:0]
Memory Controller Interface Registers
0x4000
External I/O Access Control Register 0
R/W
[31:0]
0x4004
External I/O Access Control Register 1
R/W
[31:0]
0x4008
External I/O Access Control Register 2
R/W
[31:0]
0x4010
ROM/SRAM/FLASH Control Register 0
R/W
[31:0]
0x4014
ROM/SRAM/FLASH Control Register 1
R/W
[31:0]
0x4020
ROM/SRAM/FLASH General Register
R/W
[31:0]
0x4030
SDRAM Control Register 0
R/W
[31:0]
0x4034
SDRAM Control Register 1
R/W
[31:0]
0x4038
SDRAM General Control Register
R/W
[31:0]
0x403C
SDRAM Buffer Control Register
R/W
[31:0]
0x4040
SDRAM Refresh Timer Register
R/W
[31:0]
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