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參數(shù)資料
| 型號： | K7N403609B-QI22 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 398K |
| 代理商： | K7N403609B-QI22 |
K7N403609B
128Kx36/x32 & 256Kx18 Pipelined NtRAMTM
- 3 -
Rev 1.0
November 2001
K7N401809B
K7N403209B
128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM
The K7N403609B, K7N403209B and K7N401809B are
4,718,592 bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incomming sig-
nals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released
to the output bufferes at the next rising edge of clock.
The K7N403609B, K7N403209B and K7N401809B are imple-
mented with SAMSUNG
′s high performance CMOS technol-
ogy and is available in 100pin TQFP packages. Multiple
power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
VDD=3.3V+0.165V/-0.165V Power Supply.
VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no datacon-
tention.
Α interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A Package.
Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Symbol
-25
-22
-20
Unit
Cycle Time
tCYC
4.0
4.4
5.0
ns
Clock Access Time
tCD
2.4
2.6
2.8
ns
Output Enable Access Time
tOE
2.4
2.6
2.8
ns
WE
BWx
CLK
CKE
CS1
CS2
ADV
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
ADDRESS
REGISTER
C
O
N
T
R
O
L
O
G
IC
A
′0~A′1
36/32 or 18
DQPa ~ DQPd
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
O
N
T
R
O
L
R
E
G
IS
T
E
R
K
A [0:16]or
A [0:17]
LBO
A 2~A 16 or A2 ~A 17
A0 ~A 1
(x=a,b,c,d or a,b)
128Kx36/32 , 256Kx18
MEMORY
ARRAY
N tRAM TM
and No Turnaround Random Access Memory are trademarks of Samsung,
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