參數資料
型號： TLC320AD535I
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： DUAL CHANNEL VOICE/DATA CODEC
中文描述： 雙通道語音/數據編解碼器
文件頁數： 47/84頁
文件大?。?/td> 447K
代理商： TLC320AD535I
3–8
3.6
Timing Requirements and Specifications in Master Mode
3.6.1
Recommended Input Timing Requirements for Master Mode, V
DD
= 5 V
MIN
NOM
MAX
UNIT
tr(MCLK)
tf(MCLK)
Master clock rise time
5
ns
Master clock fall time
5
ns
Master clock duty cycle
40%
60%
tw(RESET)
tsu(DIN)
th(DIN)
RESET pulse duration
1 MCLK
DIN setup time before SCLK low (see Figure 4–2)
25
ns
DIN hold time after SCLK low (see Figure 4–2)
20
ns
3.6.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V
DD
= 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN
TYP
MAX
UNIT
tf(SCLK)
tr(SCLK)
Shift clock fall time (see Figure 4–2)
13
18
ns
Shift clock rise time (see Figure 4–2)
13
18
ns
Shift clock duty cycle
45%
55%
td(CH-FL)
Delay time from SCLK high to FSD low
(see Figures 4–2 and 4–4 and Note 24)
5
20
ns
td(CH-FH)
Delay time from SCLK high to FS high (see Figure 4–2)
5
20
ns
td(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4–2 and 4–7)
20
ns
td(CH-DOUTZ)
Delay time from SCLK
↑
to DOUT in high-impedance state
(see Figure 4–8)
20
ns
td(ML-EL)
td(ML-EH)
tf(EL)
tr(EH)
td(MH-CH)
td(MH-CL)
All typical values are at VDD = 5 V and TA = 25
°
C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
Delay time from MCLK low to EOC low (see Figure 4–9)
40
ns
Delay time from MCLK low to EOC high (see Figure 4–9)
40
ns
EOC fall time (see Figure 4–9)
13
ns
EOC rise time (see Figure 4–9)
13
ns
Delay time from MCLK high to SCLK high
50
ns
Delay time from MCLK high to SCLK low
50
ns
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相關代理商/技術參數
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