參數(shù)資料
型號(hào)： ENC424J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 39/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 131
PIC18F2220/2320/4220/4320
14.2
Timer1 Oscillator
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated for 32 kHz crystals. See
14.3
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.4
Resetting Timer3 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
to generate
a
“Special
Event
Trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
for more information.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a Special Event Trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1:
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note:
The Special Event Triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
OSCIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 00-0 0000
PIE2
OSCIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 00-0 0000
IPR2
OSCIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111 11-1 1111
TMR3L
Timer3 Low Byte Register
xxxx xxxx uuuu uuuu
TMR3H
Timer3 High Byte Register
xxxx xxxx uuuu uuuu
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 u0uu uuuu
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
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