REV. 5.0.2 28 FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a 鈥�1鈥�." />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ST16C654CQ100-F
寤犲晢锛� Exar Corporation
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鎻忚堪锛� IC UART FIFO 64B QUAD 100QFP
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ST16C654/654D
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2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
28
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a 鈥�1鈥�.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a 鈥�1鈥�.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 12 below shows the selections. EFR bit-4
must be set to 鈥�1鈥� before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections.
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER
LEVEL
TRANSMIT
TRIGGER
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
XR16C854IJTR-F IC UART FIFO 128B QUAD 68PLCC
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鍙冩暩(sh霉)鎻忚堪
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ST16C654CQ64-0A-EVB 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 Supports C654 64 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V
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