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參數(shù)資料
| 型號(hào)： | DAC8222GPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL W/BUFF 24DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 12 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
DAC8222
–8–
REV. C
between IOUT and AGND terminals be as close to zero as practi-
cal in order to keep DAC errors to a minimum. This is normally
done by connecting AGND to the noninverting input of an op
amp and IOUT to the inverting input. The DAC’s internal resis-
tor (RFB) can be used for the feedback resistor by connecting the
op amp’s output directly to the DAC’s RFB terminal. The op
amp also provides the current-to-voltage conversion for the
DAC’s output current. The output voltage is dependent on the
DAC’s digital input code and VREF, and is given by:
VOUT = –VREF
× D/4096
where D is the digital input code integer number that is between
0 and 4095.
The DAC’s input resistance, VREF (Figure 19), is always equal
to a constant value, R. This means that VREF can be driven by a
reference voltage or current, ac or dc (positive or negative). It is
recommended that a low-temperature-coefficient external RFB
resistor be used if a current source is employed.
The DAC’s output capacitance (COUT) is code dependent and
varies from 90 pF (all digital inputs low) to 120 pF (all digital
inputs high).
Figure 19 shows a transistor switch in series with the R-2R lad-
der terminating resistor and RFB resistor. They were designed
into the DAC to binarily match the ladder leg switches and im-
prove power supply rejection and gain error temperature coeffi-
cient. The gates of these transistor switches are connected to
VDD, so that an “open-circuit” exists when VDD is not applied.
This means that an op amp’s output voltage will go to either
“rail” if powered up before the DAC. Also, RFB resistance can-
not be measured without VDD being applied.
Figure 21. Digital Input Structure For One Bit
DIGITAL SECTION
The DAC8222’s digital inputs are CMOS inserters. They were
designed to convert TTL and CMOS input logic levels into
voltage levels to drive the internal circuitry. The digital inputs
are TTL compatible at VDD = +5 V and CMOS compatible at
VDD = +15 V. The DAC8222 can use +5 V CMOS logic levels
with VDD = +12 V; however, supply current will rise to approxi-
mately 5 mA–6 mA.
Figure 21 shows the DAC’s digital input register structure for
one bit. This circuit drives the DAC register. Digital controls
φ
and
φ shown are generated from DAC A/DAC B and WR con-
trol signals.
As shown in Figure 21, these inputs are electrostatic-discharge
protected with two internal distributed diodes; they are con-
nected between VDD and DGND. Each digital input has a typi-
cal input current of less than 1 nA.
When the digital inputs are in the region of +1.2 V to +2.8 V
(peaking at +1.8 V) using a +5 V power supply or in the region
of +1.7 V to +12 V (peaking at +3.9 V) with a +15 V power
supply, the input register transistors are operating in their linear
region and draw current from the power supply. It is therefore,
recommended that the digital input voltages be as close to the
supply rails (VDD and DGND) as is practically possible to keep
supply currents at a minimum. The DAC8222 may be operated
with any supply voltage between the range of +5 V to +15 V.
INTERFACE CONTROL LOGIC
The DAC8222’s input control logic circuitry is shown in Figure
22. Note how the
WR signal is used in conjunction with DAC
A/ DAC B to load data into either input register. LDAC loads
data from the input registers to the DAC register; the DAC’s
analog output voltage is determined by the data contained in
each DAC register.
The truth table for the DAC registers is shown in the Mode Se-
lection Table. Note how the input register is transparent when
WR is low and LDAC is high, and that the DAC register is
transparent when
WR is high and LDAC is low (LDAC updates
the DAC’s analog output voltage). The DAC is transparent
from input to output when
WR and LDAC are both low, and
the DAC is latched (input and output is not being updated)
when
WR and LDAC are both high.
Figure 22. Input Control Logic
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| DAC8228FP | 功能描述:IC DAC 8BIT DUAL V-OUT 20-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| DAC8228FPZ | 功能描述:IC DAC 8BIT DUAL V-OUT 20DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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