原裝nxp邏輯ic 74hc595n

 features
· 8-bit serial input
· 8-bit serial or parallel output
· storage register with 3-state outputs
· shift register with direct clear
· 100 mhz (typical) shift out frequency
· esd protection:
hbm eia/jesd22-a114-a exceeds 2000 v
mm eia/jesd22-a115-a exceeds 200 v.
applications
· serial-to-parallel data conversion
· remote control holding register.
description
the 74hc/hct595 are high-speed si-gatecmosdevices
and are pin compatible with low power schottky ttl
(lsttl). they are specified in compliance with jedec
standard no. 7a.
the 74hc/hct595 is an 8-stage serial shift register with a
storage register and 3-state outputs. the shift register and
storage register have separate clocks.
data is shifted on the positive-going transitions of the
sh_cp input. the data in each register is transferred to
the storage register on a positive-going transition of the
st_cp input. if both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.
the shift register has a serial input (ds) and a serial
standard output (q7’) for cascading. it is also provided
with asynchronous reset (active low) for all 8 shift
register stages. the storage register has 8 parallel 3-state
bus driver outputs. data in the storage register appears at
the output whenever the output enable input (oe) is low.