參數(shù)資料
型號： DS3120
廠商： Maxim Integrated Products
文件頁數(shù)： 6/133頁
文件大?。?/td> 0K
描述： IC FRAMER T1 28-CHAN 0-70C DEG
標(biāo)準(zhǔn)包裝： 1
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 300mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 316-BGA
包裝： 管件
DS3112
103 of 133
11.2
Instruction Register and Instructions
The Instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift data one
stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR
state with JTMS high will move the controller to the Update-IR state. The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS3112 and their respective operational binary codes are shown in
Table 11-1. Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Bypass
011
HIGH-Z
Bypass
100
IDCODE
Device Identification
001
11.2.1 SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of
the DS3112 can be sampled at the Boundary Scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS3112 to shift data
into the Boundary Scan register via JTDI using the Shift-DR state.
11.2.2 EXTEST
EXTEST allows testing of all interconnections to the DS3112. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The Boundary Scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the Boundary Scan register.
11.2.3 BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the
device's normal operation.
11.2.4 IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register's parallel output. The device ID code will always have a one in the LSB position.
The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed
by 16 bits for the device and 4 bits for the version. The device ID code for the DS3112 is 0000B143h.
11.2.5 HIGHZ
All digital outputs will be placed into a high impedance state. The Bypass Register will be connected
between JTDI and JTDO.
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