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DS26401 Octal T1/E1/J1 Framer
20
Signal Name:
TSYSCLK (1–8)
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store
function is enabled. Should be tied low in applications that do not use the transmit-side elastic store.
Signal Name:
TCHBLK/CLK (1–8)
Signal Description:
Transmit Channel Block
Signal Type:
Output
A dual function pin. TCHBLK is a user programmable output that can be forced high or low during any of the
channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or
ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel
loopback, and for per-channel conditioning.
TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be
programmed to output a gated bit clock useful for fractional services. Synchronous with TCLK when the transmit-
side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful
for parallel-to-serial conversion of channel data.
5.3 Parallel Control Port
Signal Name:
ADDR[11:0]
Signal Description:
Microprocessor Address Bus
Signal Type:
Input
This bus selects a specific register in the DS26401 during read/write access. ADDR11 is the MSB and ADDR0 is
the LSB.
Signal Name:
DATA[7:0]
Signal Description:
Microprocessor Data Bus
Signal Type:
Input/Output
This 8-bit, bidirectional data bus is used for read/write access of the DS26401 information and control registers.
DATA7 is the MSB and DATA0 is the LSB.
Signal Name:
CS
Signal Description:
Chip Select
Signal Type:
Input
This active-low signal is used to qualify register read/write accesses. The RD and WR signals are qualified with CS.
Signal Name:
RD (DS)
Signal Description:
Read Enable
Signal Type:
Input
This active-low signal along with CS qualifies read access to one of the DS26401 registers. The DS26401 drives the
DATA bus with the contents of the addressed register while RD and CS are both low.
Signal Name:
WR (R/W)
Signal Description:
Write Enable
Signal Type:
Input
This active-low signal along with CS qualifies write access to one of the DS26401 registers. Data at DATA[7:0] is
written into the addressed register at the rising edge of WR while CS is low.
Signal Name:
INT
Signal Description:
Interrupt
Signal Type:
Output
This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INT is deasserted
when all interrupts have been acknowledged and serviced.