參數(shù)資料
型號: DS21Q44T
廠商: Maxim Integrated Products
文件頁數(shù): 34/105頁
文件大小: 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
標準包裝: 72
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q44
34 of 105
SYMBOL
POSITION
NAME AND DESCRIPTION
TESALGN
CCR5.5
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 13 for details.
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
RCM3
CCR5.3
Receive Channel Monitor Bit 3.
RCM2
CCR5.2
Receive Channel Monitor Bit 2.
RCM1
CCR5.1
Receive Channel Monitor Bit 1.
RCM0
CCR5.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
(LSB)
––––
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
CCR6.7
Not Assigned. Should be set to zero when written
CCR6.6
Not Assigned. Should be set to zero when written
CCR6.5
Not Assigned. Should be set to zero when written
CCR6.4
Not Assigned. Should be set to zero when written
CCR6.3
Not Assigned. Should be set to zero when written
TCLKSRC
CCR6.2
Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RESR
CCR6.1
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
TESR
CCR6.0
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
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