參數(shù)資料
型號(hào): DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 64/136頁
文件大小: 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: RS08
類型: MCU
適用于相關(guān)產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
33
4.7.2
Flash Control Register (FLCR)
4.8
Page Select Register (PAGESEL)
There is a 64-byte window ($00C0–$00FF) in the direct-page reserved for paging access. Programming
the page select register determines the corresponding 64-byte block on the memory map for direct-page
access. For example, when the PAGESEL register is programmed with value $08, the high page registers
($0200–$023F) can be accessed through the paging window ($00C0–$00FF) via direct addressing mode
instructions.
765
432
10
R
0
000
HVEN
MASS
0
PGM1
W
Reset
0
000
0
= Unimplemented or Reserved
Figure 4-4. Flash Control Register (FLCR)
Table 4-3. FLCR Field Descriptions
Field
Description
3
HVEN
High Voltage Enable — This read/write bit enables high voltages to the Flash array for program and erase
operations. HVEN can be set only if either PGM = 1 or MASS = 1 and the proper sequence for program or erase
is followed.
0 High voltage disabled to array.
1 High voltage enabled to array.
2
MASS
Mass Erase Control Bit — This read/write bit configures the memory for mass erase operation.
0 Mass erase operation not selected.
1 Mass erase operation selected.
0
PGM1
1 When Flash security is engaged, writing to PGM bit has no effect. As a result, Flash programming is not allowed.
Program Control Bit — This read/write bit configures the memory for program operation. PGM is interlocked
with the MASS bit such that both bits cannot be equal to 1 or set to 1 at the same time.
0 Program operation not selected.
1 Program operation selected.
765
432
10
R
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
W
Reset
0
000
100
0
Figure 4-5. Page Select Register (PAGESEL)
Table 4-4. PAGESEL Field Descriptions
Field
Description
7:0
AD[13:6]
Page Selector— These bits define the address line bit 6 to bit 13, which determines the 64-byte block boundary
of the memory block accessed via the direct page window. See Figure 4-6 and Table 4-5.
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