
CY28405-2
Document #: 38-07511 Rev. *C
Page 6 of 16
Byte 4: Control Register
Bit
7
@Pup
0
Name
Description
USB_48
USB_48MHz Drive Strength Control
0 = Low Drive Strength, 1 = High Drive Strength
USB_48MHz Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
USB_48
5
0
PCIF2
4
0
PCIF1
3
0
PCIF0
2
1
PCIF2
1
1
PCIF1
0
1
PCIF0
Byte 5: Control Register
Bit
7
@Pup
1
Name
Description
DOT_48
DOT_48MHz Output Enable
0 = Disabled, 1 = Enabled
Reserved, set = 1
3V66_3/VCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
3V66_3/VCH Output Enable
0 = Disabled, 1 = Enabled
Reserved, set = 1
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
0
Reserved
3V66_3/VCH
4
1
3V66_3/VCH
3
2
1
1
Reserved
3V66_2
1
1
3V66_1
0
1
3V66_0
Byte 6: Control Register
Bit
7
6
5
@Pup
0
0
0
Name
Description
Reserved
Reserved
CPUC0, CPUT0
CPUC1, CPUT1
CPUT_ITP,CPUC_ITP
SRCT, SRCC
Reserved, set = 0
Reserved, set = 0
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT/C Frequency Select
0 = 100Mhz, 1 = 200MHz
Spread Spectrum Mode
0 = down (default), 1 = center
3
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP