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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 84/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
8-14
CTM
REFERENCE
DOUBLE ACTION SUBMODULE (DASM)
For More Information On This Product,
Go to: www.freescale.com
8
8.6.1
DASMSIC — DASM status/interrupt/control register
FLAG — Flag status bit
This status bit indicates whether or not an input capture or output compare event has occurred. If
the IL field is non-zero, an interrupt request is generated when the FLAG bit is set.
1 (set)
–
An input capture or output compare event has occurred.
0 (clear) –
An input capture or output compare event has not occurred.
–
–
In the DIS mode, the FLAG bit is cleared.
In the IPWM mode, the FLAG bit is set each time there is a capture on
channel A.
In the IPM mode, the FLAG bit is set each time there is a capture on channel
A, except for the first time.
In the IC mode, the FLAG bit is set each time there is a capture on channel A.
In the OCB mode (i.e. when MODE0 = 0), the FLAG bit is only set each time
there is a successful comparison on channel B. In the OCAB mode (i.e.
when MODE0 = 1), the FLAG bit is set each time there is a successful
comparison on either channel A or B.
In the OPWM mode, the FLAG bit is set whenever there is a successful
comparison on channel A.
–
–
–
–
This flag bit is set only by the hardware and is cleared only by the software or by a system reset.
The software can clear the FLAG bit either by writing a zero to it, having first read the bit as a one,
or by selecting the DIS mode.
To clear the flag, the software must first read the bit (as ‘one’) then write a ‘zero’ to the bit.
Note:
The flag clearing mechanism will work only if no flag setting event occurs between the
read and write operations; if a FLAG setting event occurs between the read and write
operations, the FLAG bit will not be cleared.
(1) Offset fromthe base address of the DASMsubmodule.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DASMSIC
$00
(1)
FLAG
IL2
IL1
IL0
IARB3
WOR
BSL
IN
FORCA FORCB EDPOL MODE3 MODE2 MODE1 MODE0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
.
Freescale Semiconductor, Inc.
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