
MOTOROLA
7-10
CTM
REFERENCE
SINGLE ACTION SUBMODULE (SASM)
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7
In OCT mode, the EDOUT bit has no effect. However, the force function is still available and will
force the value of the EDOUT bit to appear on the output pin.
In OP mode, the value of the EDOUT bit is output to the corresponding pin. Reading EDOUT
returns the previous value written.
The EDOUT bit is cleared by reset.
MODE1, MODE0 — SASM operating mode select bits
These control bits select the mode of operation of the SASM channel, as shown in the following
table.
MODE1 and MODE0 are cleared by reset.
7.5.2
SDATA — SASM data register A
SDATA is the 16-bit read-write register associated with channel A. In IC mode, SDATA contains the
last captured value. In the OC, OCT and OP modes, it is loaded with the value of the next output
compare. SDATA is not affected by reset.
7.5.3
SICB — SASM status/interrupt/control register B
This register contains the control and status bits for SASM channel B. The bits it contains are
identical to those in SICA, with the exception of the IL[2:0], IARB3 and IEN which apply to both
(1) Offset fromthe base address of the SASMsubmodule.
MODE1
0
0
1
1
MODE0
SASMchannel operating mode
Input capture (IC)
Output port (OP)
Output compare (OC)
Output compare and toggle (OCT)
0
1
0
1
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDATA
$02
(1)
MSB
LSB
Reset:
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
F
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Freescale Semiconductor, Inc.