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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 29/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
1-9
FUNCTIONAL OVERVIEW
For More Information On This Product,
Go to: www.freescale.com
1
The gated mode of operation can be used to measure the pulse width or period of an input signal.
When the input to the pulse accumulator is active, the counter begins counting the input clock.
When the signal is negated it stops counting. If the counter is set to zero before the pulse starts,
the count value multiplied by the clock period gives the width of the input pulse to the nearest clock
period. This could be used to determine how long a stimulus is present.
In an 8-bit pulse accumulator only 255 events can be counted before the counter overflows; the
overflow flag can be used to extend the counter range beyond this value if required.
1.9
Pulse width modulation (PWM) concepts
A PWM waveform is created when the mark-to-space ratio of a periodic rectangular signal can be
varied. If the waveform can be incrementally changed by 1/65536 of its period, it has 16 bits of
resolution (see Figure 1-8).
A typical 16-bit PWM system (Motorola’s General Purpose Timer, or GPT) is shown in Figure 1-9.
Each time the counter overflows from $FFFF to $0000, the zero detector sets the output latch
(output pin in high state). The zero detector is used as the reference to start the high time. As the
counter is incremented, the counter value is compared with the contents of the pulse width register.
When the comparator detects a match, the latch is reset. By changing the value in the pulse width
register, the duty cycle is continuously variable in 1/65536 increments.
If the pulse width register contains $0000, the output latch will always be in the reset condition
(output pin in low state). If the pulse width register is loaded with $0001, the output latch will be set
for one count before being reset for the remainder of the period. If the register contains $8000
(32768 in decimal), the latch will be set for 32768 counts of the timer before being reset, resulting
in a duty cycle of 50%. Provision is usually made to allow a 100% duty cycle (output latch always
set; output pin always high) to be generated.
Varying the input clock frequency to the PWM counter also varies the period of the PWM signal.
Figure 1-8
PWM example waveforms
65536 increments
1/65536
32768/65536
F
.
Freescale Semiconductor, Inc.
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