參數(shù)資料
型號: CTMRM
英文描述: Configurable Timer Module Reference Manual
中文描述: 配置定時器模塊參考手冊
文件頁數(shù): 127/164頁
文件大?。?/td> 1148K
代理商: CTMRM
CTM
REFERENCE
MOTOROLA
A-5
REGISTER AND BIT SUMMARY
For More Information On This Product,
Go to: www.freescale.com
A
A.3.1.4
DRVA, DRVB — Drive time base bus bits
Warning:
It is not recommended that the two time base buses be driven at the same time.
A.3.1.5
IN — Input pin status bit
This read-only status bit reflects the logic state of the FCSM input pin CTMC
A.3.1.6
CLK[2:0] — Counter clock select bits
A.3.2
FCSMCNT — FCSM counter register
(1) Offset fromthe base address of the FCSMsubmodule.
DRVA
0
0
1
1
DRVB
0
1
0
1
Bus selected
Neither time base bus A nor time base bus B is driven
Time base bus B is driven
Time base bus A is driven
Both time base bus A and time base bus B are driven
CLK2
0
0
0
0
1
1
1
1
CLK1
0
0
1
1
0
0
1
1
CLK0 Free running counter clock source
0
Prescaler output 1 (
÷
2 or
÷
3)
1
Prescaler output 2 (
÷
4 or
÷
6)
0
Prescaler output 3 (
÷
8 or
÷
12)
1
Prescaler output 4 (
÷
16 or
÷
24)
0
Prescaler output 5 (
÷
32 or
÷
48)
1
Prescaler output 6 (
÷
64 to
÷
768)
0
CTMC pin input, negative edge
1
CTMC pin input, positive edge
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCSMCNT
$02
(1)
MSB
LSB
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
.
Freescale Semiconductor, Inc.
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