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參數(shù)資料
| 型號： | CGS702V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI |
| 中文描述： | 702 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 181K |
| 代理商： | CGS702V |
CGS702 AC Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
e
5V, T
A
e
25
§
C
Symbol
Parameter
V
CC
e
4.5V to 5.5V
f
IN
e
25 MHz to 40 MHz
T
e
0
§
C to 70
§
C
C
L
e
Circuit 1 and 2
R
L
e
Circuit 1 and 2
Units
Notes
Min
Typ
Max
t
RISE
Output Rise
CLK4
CLK2
CLK1
0.8V to 2.6V
1.0V to V
CC
b
1.0V
1.0V to V
CC
b
1.0V
ns
(Note 1)
2.0
t
FALL
Output Fall
CLK4
CLK2
CLK1
2.6V to 0.8V
V
CC
b
1.0V to 1.0V
V
CC
b
1.0V to 1.0V
ns
(Note 1)
2.0
t
SKEW
Maximum
Edge-to-Edge
Output Skew
a
to
a
Edges
a
to
a
Edges
a
to
a
Edges
CLK1DCLK1
CLK1DCLK4
CLK2DCLK4
500
1000
1500
ps
(Note 2)
t
LOCK
Time to Lock the Output to the XTALIN Input
100
m
s
t
CYCLE
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
49
49
35
51
51
65
%
(Note 3)
J
LT
Output Jitter (Long Term)
300
ps
(Notes 4, 5)
J
CC
Output Jitter
(Cycle to Cycle)
CLK1
b
75
a
75
ps
(Notes 4, 5, 6)
CLK2
g
250
ps
(Notes 4, 5, 7)
CLK4
g
250
ps
(Notes 4, 5, 7)
F
MIN
Minimum XTALIN Frequency
15
MHz
F
MAX
Maximum XTALIN Frequency
43
MHz
Note 1:
t
RISE
and t
FALL
parameters are measured at the pin of the device
Note 2:
Skew is measured at 50% of V
CC
for CLK1 and CLK2. While it is measured at 1.4V for CLK4.
Note 3:
Output duty cycle is measured at V
DD
/2 for CLK1 and CLK2. While it is measured at 1.4V for CLK4.
Note 4:
Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles.
It is also measured at output levels of V
CC
/2 . Refer to Figure 2 for further explanation.
Note 5:
The GNDA pins of the 702 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB.
Also the V
CCA
pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for V
CCA
pin.
Note 6:
Cycle to Cycle Jitter is measured at V
CC/2
.
Note 7:
Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25
§
C, 5V measured
@
V
CC/2
.
TL/F/12386–4
Circuit 1. Test Circuit for CLK1 and CLK2
TL/F/12386–5
Circuit 2. Test Circuit for CLK4
5
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