參數(shù)資料
型號: CGS702V
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI
中文描述: 702 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 2/10頁
文件大小: 181K
代理商: CGS702V
General Description
(Continued)
Also included, are two EXTSEL and EXTCLK pins to allow
testing the chip via an external source. The EXTSEL pin,
once set to high, causes the External-ClockDMux to
change its input from the output of the VCO and Counter to
the external clock signal provided via EXTCLK input pin.
CLK1SEL pin changes the output frequency of the CLK1D
0,6 outputs. During normal operation, when CLK1SEL pin is
high, these outputs are at the same frequency as the input
crystal oscillator, while CLK2 and CLK4 outputs are at twice
and four times the input frequency respectively.
Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.
In addition two other pins are added for increasing the test
capability. SKWSEL and SKWTST pins allow testing of the
counter’s output and skew of the output drivers by bypass-
ing the VCO. In this test mode CLK4 frequency is the same
as SKWTST input frequency, while CLK2 is
(/2
and CLK1
frequencies are
(/4
respectively (refer to the truth table). In
addition CLK1SEL functionality is also true under this test
condition.
Block Diagram
TL/F/12386–2
2
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