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參數(shù)資料
| 型號(hào)： | CGS701AV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver |
| 中文描述： | 701 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 162K |
| 代理商： | CGS701AV |
CGS701A
AC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at V
CC
e
5V, T
A
e
25
§
C.
Symbol
Parameter
V
CC
e
4.5V–5.5V
F
IN
e
25 to 40 MHz
T
e
0
§
C to
a
70
§
C
C
L
e
Circuit 1
R
L
e
Circuit 1
Units
Notes
Min
Typ
Max
t
rise
Output Rise
CLK4
CLK2
CLK1
0.8V to 2.6V
1.0V to V
CC
b
1.0V
1.0V to V
CC
b
1.0V
(Note 1, 7)
2.0
ns
All
0.8V to 2.0V
1.5
t
fall
Output Fall
CLK4
CLK2
CLK1
2.6V to 0.8V
V
CC
b
1.0V to 1.0V
V
CC
b
1.0V to 1.0V
(Note 1, 7)
2.0
ns
All
0.8V to 2.0V
1.5
t
SKEW
Maximum Edge-to-
Edge Output Skew
a
to
a
Edges
a
to
a
Edges
a
to
a
Edges
CLK1DCLK1
CLK1DCLK4
CLK2DCLK4
400
1000
1000
(Note 2, 7)
ps
t
LOCK
Time to Lock the Output to the Synch Input
20
100
m
s
t
CYCLE
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
49
49
35
51
51
65
(Note 3, 7)
%
J
LT
Output Jitter (Long Term)
0.3
ns
(Note 4, 7)
t
PD
Propogation Delay from XTALIN to FBKOUT
b
0.3
a
0.3
ns
(Notes 2, 4, 5, 6, 7)
F
MIN
Minimum XTALIN Frequency
15
MHz
F
MAX
Maximum XTALIN Frequency
43
MHz
Note 1:
t
rise
and t
fall
parameters are measured at the pin of the device.
Note 2:
Skew is measured at 50% of V
CC
for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design.
Note 3:
Output duty cycle is measured at V
DD
/2 for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design.
Note 4:
Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles.
It is also measured at output levels of V
CC
/2. Refer to Figure 3 for further explanation.
Note 5:
Measured from the ref. input to any output pin. The length of the feedback and XTALIN traces will impact this delay time.
Note 6:
This parameter includes pin-to-pin skew, longterm jitter over 1000 cycles, part-to-part variation as well as propagation delay thru the device.
Note 7:
The GNDA pins of the 701 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB.
Also the V
CCA
pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for the V
CCA
pin.
Circuit 1. Test Circuit
TL/F/11920–4
http://www.national.com
5
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