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參數(shù)資料
| 型號： | CGS701AV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver |
| 中文描述： | 701 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 162K |
| 代理商： | CGS701AV |
CGS701A
General Description
(Continued)
CLK1SEL pin changes the output frequency of the
CLK1D0 thru CLK1D5 outputs. During normal operation,
when CLK1SEL pin is high, these outputs are at the same
frequency as the input crystal oscillator, while CLK2 and
CLK4 outputs are at twice and four times the input frequen-
cy respectively.
Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.
In addition, another pin is added for increasing the test ca-
pability. SKWSEL pin allows testing of the counter’s output
and skew of the output drivers by bypassing the VCO. In this
test mode CLK4 frequency is the same as SKWTST input
frequency, while CLK2 is 1/2 and CLK1 frequencies are 1/4
respectively (refer to the Truth Table). In addition CLK1SEL
functionality is also true under this test condition.
Block Diagram
TL/F/11920–2
http://www.national.com
2
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