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參數(shù)資料
| 型號(hào)： | CGS700TV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
| 中文描述： | 商業(yè)低偏移鎖相環(huán)1至9的CMOS時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | CGS700TV |
CGS700
(Continued)
AC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at V
CC
e
5V, T
A
e
25
§
C
Symbol
Parameter
V
CC
e
4.5V–5.5V
F
IN
e
25 MHz–40 MHz
T
A
e
0
§
C–70
§
C
C
L
e
Circuit 1 and 2
R
L
e
Circuit 1 and 2
Units
Notes
Min
Typ
Max
t
rise
Output Rise
CLK4
CLK2
CLK1
0.8V–2.6V
1.0V–V
CC
b
1.0V
1.0V–V
CC
b
1.0V
2.0
ns
(Notes 1, 5)
ALL
0.8V–2.0V
1.5
t
fall
Output Fall
CLK4
CLK2
CLK1
2.6V–0.8V
V
CC
b
1.0V–1.0V
V
CC
b
1.0V–1.0V
2.0
ns
(Notes 1, 5)
ALL
2.0V–0.8V
1.5
t
skew
Maximum Edge-
to-Edge Output
Skew
a
to
a
Edges
a
to
a
Edges
a
to
a
Edges
CLK1DCLK1
CLK1DCLK4
CLK2DCLK4
400
1000
1000
ps
(Notes 2, 5)
t
lock
Time to Lock the Output to the Synch Input
100
m
s
t
cycle
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
49
49
35
51
51
65
%
(Notes 3, 5)
J
LT
Output Jitter (Long Term)
0.3
ns
(Notes 4, 5)
F
MIN
Minimum XTALIN Frequency
15
MHz
F
MAX
Maximum XTALIN Frequency
43
MHz
Circuit 1. Test Circuit for CLK1 and CLK2
TL/F/11955–4
Circuit 2. Test Circuit for CLK4
TL/F/11955–9
http://www.national.com
4
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|---|---|
| CGS700V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
| CGS701ATV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver |
| CGS701AV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver |
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| CGS701V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
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