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參數(shù)資料
| 型號(hào)： | CGS700TV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
| 中文描述： | 商業(yè)低偏移鎖相環(huán)1至9的CMOS時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 126K |
| 代理商： | CGS700TV |
General Description
(Continued)
Also included, are two EXTSEL and EXTCLK pins to allow
testing the chip via an external source. The EXTSEL pin,
once set to high, causes the External-ClockDMux to
change its input from the output of the VCO and Counter to
the external clock signal provided via EXTCLK input pin.
CLK1SEL pin changes the output frequency of the
CLK1D0, CLK1D6 outputs. During normal operation, when
CLK1SEL pin is high, these outputs are at the same fre-
quency as the input crystal oscillator, while CLK2 and CLK4
outputs are at twice and four times the input frequency re-
spectively.
Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.
In addition two other pins are added for increasing the test
capability. SKWSEL and SKWTST pins allow testing of the
counter’s output and skew of the output drivers by bypass-
ing the VCO. In this test mode CLK4 frequency is the same
as SKWTST input frequency, while CLK2 is
(/2
and CLK1
frequencies are
(/4
respectively (refer to the truth table). In
addition CLK1SEL functionality is also true under this test
condition.
Typical Application
TL/F/11955–3
Block Diagram
CGS700
TL/F/11955–2
Truth Table
Input
Output
CLK1
SEL
EXT
SEL
EXT
CLK
SKW
SEL
SKW
TST
TRI-STATE
CLK4
CLK2
CLK1
*
H
*
L
L
X
L
X
H
4
c
f
IN
4
c
f
IN
é
2
c
f
IN
2
c
f
IN
é
f
IN
L
X
L
X
H
2
c
f
IN
é
X
H
é
X
X
H
H
L
X
H
é
H
1
c
f
tst
1
c
f
tst
(/2
c
f
tst
(/2
c
f
tst
(/4
c
f
tst
(/2
c
f
tst
L
L
X
H
é
H
X
X
X
X
X
L
Z
Z
Z
*
Steady State phase, frequency lock.
http://www.national.com
2
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| CGS700V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Commercial Low Skew PLL 1 to 9 CMOS Clock Driver |
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