參數(shù)資料
型號： DSPIC33FJ16GP304T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 21/176頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 16K 44TQFP
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 1,200
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ16GP304T-I/PTTR
115
AT89C5131
4136C–USB–04/05
USB Device Firmware
Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip
Flash memory of the AT89C5131. This allows the implementation of product enhance-
ments and patches to devices that are already in the field. Two different configurations
and descriptor sets are used to support DFU functions. The Run-Time configuration co-
exists with the usual functions of the device, which may be USB Mass Storage for the
AT89C5131. It is used to initiate DFU from the normal operating mode. The DFU config-
uration is used to perform the firmware update after device re-configuration and USB
reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to
support DFU services in both configurations.
The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes,
which is the size of the FIFO implemented for endpoint 0.
Description
The USB device controller provides the hardware that the AT89C5131 needs to inter-
face a USB link to a data flow stored in a double port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of
the AT89C5131 PLL (see Section “PLL”, page 20) divided by a clock prescaler. This
clock is used to generate a 12 MHz Full-speed bit clock from the received USB differen-
tial data and to transmit data according to full speed USB device tolerance. Clock
recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with
the jitter specification of the USB bus.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-
ing, CRC generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) realizes the interface between the data flow and
the Dual Port RAM.
Figure 53. USB Device Controller Block Diagram
SIE
DPLL
USB
D+/D-
Buffer
UFI
12 MHz
48 MHz +/- 0.25%
D+
Up to 48 MHz
UC_sysclk
C51
Microcontroller
Interface
D-
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